The present invention is directed to semiconductor devices incorporating junctions of varying conductivity types and methods of making such devices. More specifically, the present invention is directed to vertical replacement-gate (VRG) junction field-effect transistor devices and methods for fabricating integrated circuits incorporating such devices.
Enhancing semiconductor device performance and increasing device density (the number of devices per unit area), continue to be important objectives of the semiconductor industry. Device density is increased by making individual devices smaller and packing devices more compactly. But, as the device dimensions (also referred to as the feature size or design rules) decrease, the methods for forming devices and their constituent elements must be adapted. For instance, production device sizes are currently in the range of 0.25 microns to 0.12 microns, with an inexorable trend toward smaller dimensions. However, as the device dimensions shrink, certain manufacturing limitations arise, especially with respect to the lithographic processes. In fact, current lithographic processes are nearing the point where they are unable to accurately manufacture devices at the required minimal sizes demanded by today""s device users.
Currently most metal-oxide-semiconductor field effect transistors (MOSFETs) are formed in a lateral configuration, with the current flowing parallel to the major plane of the substrate or body surface. As the size of these MOSFET devices decreases to achieve increased device density, the fabrication process becomes increasingly difficult. In particular, the lithographic process for creating the gate channel is problematic, as the wavelength of the radiation used to delineate an image in the lithographic pattern approaches the device dimensions. Therefore, for lateral MOSFETs, the gate length is approaching the point where it cannot be precisely controlled through the lithographic techniques.
Like MOSFETs, junction field-effect transistors (JFETs) have been formed using lithographically defined channel lengths. As the channel length decreases to increase device density, the channel length may not be controllable using conventional photolithographic techniques. Instead, expensive x-ray and electron beam lithographic equipment may be required for the formation of both MOSFETs and JFETs with state-of-the-art channel lengths.
Generally, integrated circuits comprise a plurality of active devices, including MOSFETs, JFETs and bipolar junction transistors, as well as passive components such as resistors and capacitors. Commonly owned U.S. Pat. Nos. 6,027,975 and 6,197,441, which are hereby incorporated by reference, teach certain techniques for the fabrication of vertical replacement gate (VRG) MOSFETs. It is therefore advantageous to fabricate JFETs using similar and compatible processing steps as those employed for the fabrication of MOSFETs to reduce integrated circuit fabrication costs.
To provide further advances in the fabrication of JFETs having gate lengths precisely controlled through a deposited film thickness, an architecture is provided for fabricating vertical replacement gate (VRG) JFET devices.
According to one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first doped region formed therein. A second doped region of a different conductivity type than the first region is formed over the first region. A third doped region is formed over the second doped region, with a different conductivity type than the second doped region.
The first region is a source/drain region of a junction field-effect transistor, and the second doped region is the channel. The second source/drain region is formed over the channel and comprises the third doped region.
In an associated method of manufacture, an integrated circuit structure is fabricated by providing a semiconductor layer suitable for device formation and having a first surface formed along a first plane. For a JFET device, a first device region is formed in the semiconductor layer, wherein the device region is selected from among a source and a drain region. A gate region for the JFET is formed above the first device region. In fabricating the vertical JFET, the gate length is precisely controlled through the use of a sacrificial layer. Both JFETs and MOSFETs can be fabricated using the same basic fabrication process.
A JFET fabricated according to the teachings of the present invention provides a uniform depletion layer (or a uniform pinch-off condition) because the gate completely surrounds the channel and the channel is uniformly doped along a horizontal cross-section. In the prior art, the channel is oriented horizontally and the carriers flow horizontally through it. The channel is formed by diffusion into the semiconductor substrate and thus the upper channel region has a higher doping density then the lower region. As a result, the depletion layer is not uniform along any given vertical. Also, creating dual wells in a semiconductor substrate according to the present invention allows the fabrication of closely matched JFET pairs.